Variation-Aware IC Design.

The unique model-based solution for process variability management and parametric yield enhancement Infiniscale methodology and tool set do bring the designer an innovative and high performing tool set enabling devices sizing (transistors width and length) with yield taken in consideration for each design solution proposed. With traditional design flows, designer is sizing transistors and devices to find the nominal solution that would meet the block specification. Using traditionnal flows, designer would run extensive Monte-carlo checks and corner extractions to verify that his design would yield….or not ! Infiniscale model-based methodology offers a smart way to perform a nominal sizing that would “by construction” reach the best possible yield. Yield is then verified in seconds and additionnal trade-offs or explorations can be made in a very short time.

The innovative IC process variability manager

Printed Electronics Device Modeling Today engineers who develop organic transistors, OLED or solar cells face a new challenge. Unlike the silicon based technology currently used in Microelectronics where engineers use existing Spice models to fit the behaviour of their transistors, no physical model is able to fit the behaviour of such new organic devices. GREENLys, Infiniscale modeling solution, brings this missing piece and fill the lack of physical models thanks to a Compact modeling approach.